This invention relates to a new semiconductor integrated circuit device, and more specifically, relates to a semiconductor integrated circuit device including a shift register.
In the semiconductor integrated circuit device, a shift register is one of the most important element. Usually, when a shift register having a plurality of register stages is formed on the semiconductor substrate, said stages are arranged straightly in a numerical order. For example, as shown in FIG. 5, when the first shift register is comprised of 8 stages A1, A2, A3, A4, A5, A6, A7 and A8, such stages are arranged straightly from the 1st stage A1 to the 8th stage A8. Likewise, as to the second shift register, 8 stages B1, B2, B3, B4, B5, B6, B7 and B8 are arranged straightly from the 1st stage B1 to the 8th stage B8. When the first shift register is used as a circular type shift register, input data from the input/output terminal A is supplie to the 1st stage A1 and then transferred to the 2nd stage A2 and then transferred to the 3rd, 4th, 5th, 6th, 7th and 8th stages in sequence along the arrrowed lines shown in FIG. 5. The output data from the 8th stage A8 is fed-back to the 1st stage A1 and the input/output terminal A. Also the second shift register, input data from the input/output terminal B is supplied to the 1st stage B1 and then transferred to the 2nd, 3rd, ..., 7th and 8th stages in sequence, and the output data from the 8th stage B8 is fed-back to the 1st stage B1 and the input/output terminal B. However, the above mentioned arrangement of the stages on the semiconductor substrate causes the following problems.
The first problem is that the load capacitance of each data line between the register stages becomes unequal. For example, in FIG. 5, the length of the data line from the 8th stage A8 to the 1st stage A1 is longer than that of other data lines. Consequently, the load capacitance of the former is bigger than the latter. As shown in FIG. 6, each stage is basically composed of two transfer gates Q1, Q2 and two buffers (inverter circuits) I1, I2. Therefore, in a semiconductor device shown in FIG. 5, it is necessary for the load driving capability of the output buffer I2 of the 8th stage A8 to be greater than that of the other stages. For this purpose, the size and circuit constants of the 8th stage have to be larger than that of the other stages. However, it is rather difficult to form a plurality of stages of different sizes on the semiconductor substrate. It is also possible that the size and the circuit constants of the 8th stage are designed so that the 8th stage has enough load driving capability, and the size and the circuit constants of other stages are designed so as to be equal to that of the 8th stage. However, in this case, other problems, such as total size and total power consumption cannot be reduced, etc., are caused.
The second problem is that the functional balance among several shift registers cannot be maintained. For example, in FIG. 5, the delay time of the data from the terminal A to the 1st stage A1 of the first stage register is shorter than the delay time of the data from the terminal B to the 1st stage B1 of the second shift register. This problem becomes much more serious when a shift register has a lot of stages or a lot of shift registers are arranged straightly for a long length.